EDN

Synchronous clock delivers two timing generators for SETS

Aurora, Ill. — Connor-Winfield Corp. has introduced the STC5230 single-chip synchronous clock solution for SDH, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU ...
EDN

Source-synchronous clocks pose challenges

As system-on-chip (SoC) devices are called upon to perform more computation-intensive functions, the amount of data, and the speed with which that data must be moved to and from peripheral devices, is ...
Semiconductor Engineering

Clocks Getting Skewed Up

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it’s fraught with the most problems at the ...
Electronic Design

Synchronous Clock Generator Touts Digital PLL Control

Model SCG6500 LVPECL synchronous clock generator module is said to be tha only such module to offer completely digital PLL control. The module provides one fixed, 622.08-MHz output and five ...
Electronic Design

Clock Generator Employs Digital PLL Control

The SCG6500NT synchronous clock generator is a LVPECL low-jitter, high-precision, phase-lock-loop frequency translator. According to the company, this clock generator provides designers with the ...
TechRepublic

Dynamic Power Reduction of Synchronous Digital Design by Using of Efficient Clock Gating Technique

Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits. One of the ways to achieve this is by masking the clock that goes to the idle portion of the ...